Qcom IPQ40xx Device Tree Overview
Table of Contents
- 4 cores of CPU
- clocks: sleep clk and xo
- all bus definition
- Interrupt Controller
- QCA Global Counter
- Qualcomm Global Clock & Reset Controller Binding
- ARM architected timer
- MSM Restart Driver
- Qualcomm Krait Processor Sub-system (KPSS) Watchdog
- Qualcomm Atheros IPQ40xx TLMM block
- MSM Serial UARTDM
- SPS (Smart Peripheral Switch)
- Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
- Qualcomm Parallel Interface controller (QPIC) for NAND devices
- QCOM TCSR (Top Control and Status Register)
- Qualcomm Atheros SuperSpeed DWC3 USB SoC controller
- Qualcomm MSM pseudo random number generator
- Qualcomm I2C controller
- QCEDEV and QCRYPTO
- QCA WLAN Driver
- QCA Ethernet Subsystem
- MSM PCIe
- QCA LED
- ARM Performance Monitor Units
- Qualcomm SDHCI controller (sdhci-msm)
- QCA SCMRESTARTREASON
- cpufreq driver
- qcom-ipq40xx-ap.dk04.1
4 cores of CPU
The device tree allows to describe the layout of CPUs in a system through the "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining properties for every cpu.
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,arm-cortex-acc";
reg = <0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,arm-cortex-acc";
reg = <1>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,arm-cortex-acc";
reg = <2>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,arm-cortex-acc";
reg = <3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
};
};
arm,cortex-a7:Documentation/devicetree/bindings/arm/cpus.txtqcom,arm-cortex-acc:Documentation/devicetree/bindings/arm/msm/acc.txt
Application Processor Sub-system (APSS) Application Clock Controller (ACC)
The ACC provides clock, power domain, and reset control to a CPU. There is one ACC register region per CPU within the APSS remapped region as well as an alias register region that remaps accesses to the ACC associated with the CPU accessing the region.
clocks: sleep clk and xo
clocks {
gcc_sleep_clk_src: gcc_sleep_clk_src {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
all bus definition
arch/arm/boot/dts/qcom-ipq40xx-bus.dtsi
Interrupt Controller
ARM SMP cores are often associated with a GIC, providing per processor interrupts (PPI), shared processor interrupts (SPI) and software generated interrupts (SGI).
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. Secondary GICs are cascaded into the upward interrupt controller and do not have PPIs or SGIs.
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
qcom,msm-qgic2:Documentation/devicetree/bindings/arm/gic.txt
QCA Global Counter
Documentation/devicetree/bindings/clock/qca,gcnt.txt
counter {
compatible = "qcom,qca-gcnt";
reg = <0x004a1000 0x4>;
};
Qualcomm Global Clock & Reset Controller Binding
Documentation/devicetree/bindings/clock/qcom,gcc.txt
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq40xx";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
};
adcc: clock-controller@7700038 {
compatible = "qcom,adcc-ipq40xx";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x7700038 0x1DC>;
status = "disabled";
};
ARM architected timer
Documentation/devicetree/bindings/arm/arch_timer.txt
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <48000000>;
};
MSM Restart Driver
A power supply hold (ps-hold) bit is set to power the msm chipsets. Clearing that bit allows us to restart/poweroff. The difference between poweroff and restart is determined by unique power manager IC settings.
Documentation/devicetree/bindings/power_supply/msm-poweroff.txt
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
Qualcomm Krait Processor Sub-system (KPSS) Watchdog
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
watchdog@b017000 {
compatible = "qcom,kpss-wdt-ipq40xx";
reg = <0xb017000 0x40>;
interrupt-names = "bark_irq";
interrupts = <0 3 0>;
clocks = <&gcc_sleep_clk_src>;
timeout-sec = <10>;
wdt_res = <0x4>;
wdt_en = <0x8>;
wdt_bark_time = <0x10>;
wdt_bite_time = <0x14>;
status = "ok";
};
Qualcomm Atheros IPQ40xx TLMM block
Documentation/devicetree/bindings/pinctrl/qcom,ipq40xx-pinctrl.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node".
The pin configuration nodes act as a container for an abitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc.
tlmm: pinctrl@0x01000000 {
compatible = "qcom,ipq40xx-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
};
MSM Serial UARTDM
The MSM serial UARTDM hardware is designed for high-speed use cases where the transmit and/or receive channels can be offloaded to a dma-engine. From a software perspective it's mostly compatible with the MSM serial UART except that it supports reading and writing multiple characters at a time.
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <0 108 0>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
SPS (Smart Peripheral Switch)
SPS (Smart Peripheral Switch) may be used as a DMA engine to move data in either the Peripheral-to-Peripheral (a.k.a. BAM-to-BAM) mode or the Peripheral-to-Memory (a.k.a. BAM-System) mode. SPS includes BAM (Bus Access Module) hardware block, BAM DMA peripheral, and pipe memory.
Documentation/devicetree/bindings/dma/sps/sps.txt
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,device-type = <3>;
qcom,pipe-attr-ee;
};
Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
The QUP core is an AHB slave that provides a common data path (an output FIFO and an input FIFO) for serial peripheral interface (SPI) mini-core.
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
spi_0: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78b5000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 95 0>, <0 238 0>;
spi-max-frequency = <24000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core_clk", "iface_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,bam-consumer-pipe-index = <4>;
qcom,bam-producer-pipe-index = <5>;
qcom,master-id = <0>;
status = "disabled";
};
Qualcomm Parallel Interface controller (QPIC) for NAND devices
Documentation/devicetree/bindings/mtd/msm_qpic_nand.txt
qcom,nand@7980000 {
compatible = "qcom,msm-nand";
reg = <0x07980000 0x40000>,
<0x07984000 0x1A000>;
reg-names = "nand_phys",
"bam_phys";
interrupts = <0 101 0>;
interrupt-names = "bam_irq";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<91 512 0 0>,
/* Voting for max b/w on PNOC bus for now */
<91 512 400000 800000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_CLK>;
status = "disabled";
};
QCOM TCSR (Top Control and Status Register)
The TCSR provides miscellaneous control functions and status registers for Qualcomm processors.
Documentation/devicetree/bindings/soc/qcom/qcom,tcsr.txt
tcsr: tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "disabled";
};
ess_tcsr: ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
Qualcomm Atheros SuperSpeed DWC3 USB SoC controller
Documentation/devicetree/bindings/usb/qca,dwc3.txt
- QCA BALDUR Highspeed USB PHY
- QCA UNI Superspeed USB PHY
- QCA DUMMY Superspeed USB PHY
- QCA DWC3 controller wrapper
usb3_ss_phy: ssphy@0 {
compatible = "qca,uni-ssphy";
reg = <0x9a000 0x800>;
reg-names = "phy_base";
resets = <&gcc USB3_UNIPHY_PHY_ARES>;
reset-names = "por_rst";
qca,host = <1>;
qca,emulation = <0>;
status = "disabled";
};
dummy_ss_phy: ssphy@1 {
compatible = "qca,dummy-ssphy";
status = "disabled";
};
usb3_hs_phy: hsphy@a6000 {
compatible = "qca,baldur-usb3-hsphy";
reg = <0xa6000 0x40>;
reg-names = "phy_base";
resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
qca,host = <1>;
qca,emulation = <0>;
status = "disabled";
};
usb2_hs_phy: hsphy@a8000 {
compatible = "qca,baldur-usb2-hsphy";
reg = <0xa8000 0x40>;
reg-names = "phy_base";
resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
qca,host = <1>;
qca,emulation = <0>;
status = "disabled";
};
usb3: usb3@8a00000 {
compatible = "qca,dwc3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x8af8800 0x100>;
reg-names = "qscratch_base";
clocks = <&gcc GCC_USB3_MASTER_CLK>,
<&gcc GCC_USB3_SLEEP_CLK>,
<&gcc GCC_USB3_MOCK_UTMI_CLK>;
clock-names = "master",
"sleep",
"mock_utmi";
qca,host = <1>;
status = "disabled";
dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xf8000>;
interrupts = <0 132 0>;
usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
dr_mode = "host";
usb2-susphy-quirk;
usb2-host-discon-quirk;
usb2-host-discon-phy-misc-reg = <0x24>;
usb2-host-discon-mask = <0x100>;
};
};
usb2: usb2@6000000 {
compatible = "qca,dwc3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x60f8800 0x100>;
reg-names = "qscratch_base";
clocks = <&gcc GCC_USB2_MASTER_CLK>,
<&gcc GCC_USB2_SLEEP_CLK>,
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
clock-names = "master",
"sleep",
"mock_utmi";
qca,host = <1>;
status = "disabled";
dwc3@6000000 {
compatible = "snps,dwc3";
reg = <0x6000000 0xf8000>;
interrupts = <0 136 0>;
usb-phy = <&usb2_hs_phy>, <&dummy_ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
dr_mode = "host";
usb2-susphy-quirk;
usb2-host-discon-quirk;
usb2-host-discon-phy-misc-reg = <0x24>;
usb2-host-discon-mask = <0x100>;
};
};
Qualcomm MSM pseudo random number generator
Documentation/devicetree/bindings/rng/qcom,prng.txt
rng@0x00022000 {
compatible = "qcom,prng";
reg = <0x00022000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
Qualcomm I2C controller
Documentation/devicetree/bindings/i2c/i2c-msm-v2.txt
i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr", "bam_phys_addr";
reg = <0x78b7000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "qup_irq", "bam_irq";
interrupts = <0 97 0>, <0 238 0>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
qcom,clk-freq-out = <100000>;
qcom,clk-freq-in = <19050000>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
qcom,bam-pipe-idx-cons = <8>;
qcom,bam-pipe-idx-prod = <9>;
qcom,master-id = <0>;
status = "disabled";
};
QCEDEV and QCRYPTO
Documentation/devicetree/bindings/crypto/msm/qcedev.txtDocumentation/devicetree/bindings/crypto/msm/qcrypto.txt
qcom_crypto: qcrypto@8e20000 {
compatible = "qcom,qcrypto";
reg = <0x8e20000 0x20000>,
<0x8e04000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <0>;
qcom,ce-hw-shared = <1>;
qcom,ce-device = <0>;
qcom,ce-opp-freq= <125000000>;
clocks = <&gcc GCC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core_clk", "bus_clk", "iface_clk";
status = "disabled";
};
qcom_cedev: qcedev@8e20000 {
compatible = "qcom,qcedev";
reg = <0x8e20000 0x20000>,
<0x8e04000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <0>;
qcom,ce-hw-shared = <1>;
qcom,ce-device = <0>;
qcom,ce-opp-freq= <125000000>;
clocks = <&gcc GCC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core_clk", "bus_clk", "iface_clk";
status = "disabled";
};
QCA WLAN Driver
Documentation/devicetree/bindings/qca/wlan.txt
wifi_glb_tcsr: tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
wifi_noc_memtype_m0_m2_tcsr: tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
wifi0: wifi@a000000 {
compatible = "qca,wifi-ipq40xx";
reg = <0xa000000 0x200000>;
core-id = <0x0>;
resets = <&gcc WIFI0_CPU_INIT_RESET>,
<&gcc WIFI0_RADIO_SRIF_RESET>,
<&gcc WIFI0_RADIO_WARM_RESET>,
<&gcc WIFI0_RADIO_COLD_RESET>,
<&gcc WIFI0_CORE_WARM_RESET>,
<&gcc WIFI0_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init",
"wifi_radio_srif",
"wifi_radio_warm",
"wifi_radio_cold",
"wifi_core_warm",
"wifi_core_cold";
clocks = <&gcc GCC_WCSS2G_CLK>,
<&gcc GCC_WCSS2G_REF_CLK>,
<&gcc GCC_WCSS2G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc";
interrupts = <0 0x20 0x1>,
<0 0x21 0x1>,
<0 0x22 0x1>,
<0 0x23 0x1>,
<0 0x24 0x1>,
<0 0x25 0x1>,
<0 0x26 0x1>,
<0 0x27 0x1>,
<0 0x28 0x1>,
<0 0x29 0x1>,
<0 0x2a 0x1>,
<0 0x2b 0x1>,
<0 0x2c 0x1>,
<0 0x2d 0x1>,
<0 0x2e 0x1>,
<0 0x2f 0x1>,
<0 0xa8 0x0>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6",
"msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14",
"msi15", "legacy";
status = "ok";
qca,msi_addr = <0x0b006040>;
qca,msi_base = <0x40>;
};
wifi1: wifi@a800000 {
compatible = "qca,wifi-ipq40xx";
reg = <0xa800000 0x200000>;
core-id = <0x1>;
resets = <&gcc WIFI1_CPU_INIT_RESET>,
<&gcc WIFI1_RADIO_SRIF_RESET>,
<&gcc WIFI1_RADIO_WARM_RESET>,
<&gcc WIFI1_RADIO_COLD_RESET>,
<&gcc WIFI1_CORE_WARM_RESET>,
<&gcc WIFI1_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init",
"wifi_radio_srif",
"wifi_radio_warm",
"wifi_radio_cold",
"wifi_core_warm",
"wifi_core_cold";
clocks = <&gcc GCC_WCSS5G_CLK>,
<&gcc GCC_WCSS5G_REF_CLK>,
<&gcc GCC_WCSS5G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc";
interrupts = <0 0x30 0x1>,
<0 0x31 0x1>,
<0 0x32 0x1>,
<0 0x33 0x1>,
<0 0x34 0x1>,
<0 0x35 0x1>,
<0 0x36 0x1>,
<0 0x37 0x1>,
<0 0x38 0x1>,
<0 0x39 0x1>,
<0 0x3a 0x1>,
<0 0x3b 0x1>,
<0 0x3c 0x1>,
<0 0x3d 0x1>,
<0 0x3e 0x1>,
<0 0x3f 0x1>,
<0 0xa9 0x0>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6",
"msi7", "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14",
"msi15", "legacy";
status = "ok";
qca,msi_addr = <0x0b006040>;
qca,msi_base = <0x50>;
};
QCA Ethernet Subsystem
- QCA Ethernet DMA
Documentation/devicetree/bindings/net/qca-ess.txt - QCA Ethernet Switch
ESS-SWITCH is used to forward the packet among LAN, WAN and Host
processor.
Documentation/devicetree/bindings/arm/msm/ess-switch.txt - QCA Ethernet PHY mode
ess-psgmii - MDIO Interface
ipq40xx-mdio
edma@c080000 {
compatible = "qcom,ess-edma";
reg = <0xc080000 0x8000>;
qcom,page-mode = <0>;
qcom,rx_head_buf_size = <1540>;
qcom,wan_port_id_mask = <0x10>;
qcom,mdio_supported;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
interrupts = <0 65 1>,
<0 66 1>,
<0 67 1>,
<0 68 1>,
<0 69 1>,
<0 70 1>,
<0 71 1>,
<0 72 1>,
<0 73 1>,
<0 74 1>,
<0 75 1>,
<0 76 1>,
<0 77 1>,
<0 78 1>,
<0 79 1>,
<0 80 1>,
<0 240 1>,
<0 241 1>,
<0 242 1>,
<0 243 1>,
<0 244 1>,
<0 245 1>,
<0 246 1>,
<0 247 1>,
<0 248 1>,
<0 249 1>,
<0 250 1>,
<0 251 1>,
<0 252 1>,
<0 253 1>,
<0 254 1>,
<0 255 1>;
gmac0 {
local-mac-address = [000000000000];
};
gmac1 {
local-mac-address = [000000000000];
};
};
ess-switch@c000000 {
compatible = "qcom,ess-switch";
reg = <0xc000000 0x80000>; /* 512KB */
switch_access_mode = "local bus";
resets = <&gcc ESS_RESET>, <&gcc ESS_MAC1_CLK_DIS>, \
<&gcc ESS_MAC2_CLK_DIS>, <&gcc ESS_MAC3_CLK_DIS>, \
<&gcc ESS_MAC4_CLK_DIS>, <&gcc ESS_MAC5_CLK_DIS>;
reset-names = "ess_rst","ess_mac1_clk_dis", \
"ess_mac2_clk_dis","ess_mac3_clk_dis", \
"ess_mac4_clk_dis", "ess_mac5_clk_dis";
clocks = <&gcc GCC_ESS_CLK>;
clock-names = "ess_clk";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
};
ess-psgmii@98000 {
compatible = "qcom,ess-psgmii";
reg = <0x98000 0x800>; /* 2k */
psgmii_access_mode = "local bus";
resets = <&gcc ESS_PSGMII_ARES>;
reset-names = "psgmii_rst";
};
mdio@90000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,ipq40xx-mdio";
reg = <0x90000 0x64>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
MSM PCIe
Documentation/devicetree/bindings/pci/msm_pcie.txt
pcie0: qcom,pcie@80000 {
compatible = "qcom,msm_pcie";
cell-index = <0>;
qcom,ctrl-amt = <1>;
reg = <0x80000 0x2000>,
<0x99000 0x800>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40100000 0x1000>,
<0x40200000 0x100000>,
<0x40300000 0xd00000>;
reg-names = "parf", "phy", "dm_core", "elbi",
"conf", "io", "bars";
#address-cells = <0>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 141 0
1 &intc 0 142 0
2 &intc 0 143 0
3 &intc 0 144 0
4 &intc 0 145 0
5 &intc 0 146 0
6 &intc 0 147 0
7 &intc 0 148 0
8 &intc 0 149 0
9 &intc 0 150 0
10 &intc 0 151 0
11 &intc 0 152 0 >;
interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
"int_pls_pme", "int_pme_legacy", "int_pls_err",
"int_aer_legacy", "int_pls_link_up",
"int_pls_link_down", "int_bridge_flush_n","int_wake";
qcom,ep-latency = <10>;
clocks = <&gcc GCC_PCIE_AHB_CLK>,
<&gcc GCC_PCIE_AXI_M_CLK>,
<&gcc GCC_PCIE_AXI_S_CLK>;
clock-names = "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk",
"pcie_0_slv_axi_clk";
max-clock-frequency-hz = <0>, <0>, <0>;
resets = <&gcc PCIE_AXI_M_ARES>,
<&gcc PCIE_AXI_S_ARES>,
<&gcc PCIE_PIPE_ARES>,
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
<&gcc PCIE_AXI_S_XPU_ARES>,
<&gcc PCIE_PARF_XPU_ARES>,
<&gcc PCIE_PHY_ARES>,
<&gcc PCIE_AXI_M_STICKY_ARES>,
<&gcc PCIE_PIPE_STICKY_ARES>,
<&gcc PCIE_PWR_ARES>,
<&gcc PCIE_AHB_ARES>,
<&gcc PCIE_PHY_AHB_ARES>;
reset-names = "pcie_rst_axi_m_ares",
"pcie_rst_axi_s_ares",
"pcie_rst_pipe_ares",
"pcie_rst_axi_m_vmidmt_ares",
"pcie_rst_axi_s_xpu_ares",
"pcie_rst_parf_xpu_ares",
"pcie_rst_phy_ares",
"pcie_rst_axi_m_sticky_ares",
"pcie_rst_pipe_sticky_ares",
"pcie_rst_pwr_ares",
"pcie_rst_ahb_res",
"pcie_rst_phy_ahb_ares";
status = "disabled";
};
QCA LED
Documentation/devicetree/bindings/leds/leds-ipq40xx.txt
qcom: ledc@1937000 {
compatible = "qca,ledc";
reg = <0x1937000 0x20070>;
reg-names = "ledc_base_addr";
qcom,tcsr_ledc_values = <0x320193 0x14720800 0x20d 0x0 \
0x0 0xFFFFFFFF 0x0 0x7 0x7D0010 0x0 0x10482090 0x3FFFDFC>;
qcom,ledc_blink_indices_cnt = <0>;
qcom,ledc_blink_indices = <0>;
status = "disabled";
};
ARM Performance Monitor Units
ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. The interface to the PMU is part of the ARM.
Documentation/devicetree/bindings/arm/pmu.txt
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <1 7 0xf04>;
};
Qualcomm SDHCI controller (sdhci-msm)
Documentation/devicetree/bindings/mmc/sdhci-msm.txt
sdhci@7824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
interrupts = <0 123 0>, <0 138 0>;
bus-width = <8>;
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
QCA SCMRESTARTREASON
scm restart reason driver controls the collection of crashdump.
During panic/assert the notifiers registered in this driver will be kicked in and the magic cookie is set, the crashdumps are collected in apps bootloader.
Documentation/devicetree/bindings/soc/qcom/qca,scm_restart_reason.txt
qca,scm_restart_reason {
compatible = "qca,scm_restart_reason";
};
cpufreq driver
IPQ40xx SoC cpufreq driver for CPU frequency scaling.
Documentation/devicetree/bindings/cpufreq/cpufreq-qca.txt
cpu_freq_ipq40xx {
compatible = "qca,ipq40xx_freq";
clock-latency = <100000>;
qcom,cpufreq-table =
< 48000 >,
< 200000 >,
< 500000 >,
< 716000 >;
};
qcom-ipq40xx-ap.dk04.1
uart1(serial)
arch/arm/boot/dts/qcom-ipq40xx-hsuart.dtsi
msm-hsuart-v14: Documentation/devicetree/bindings/tty/serial/msm_serial_hs.txt
uart1:uart@78b0000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0x78b0000 0x200>,
<0x7884000 0x23000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq";
#address-cells = <0>;
interrupt-parent = <&uart1>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 108 0
1 &intc 0 238 0>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
qcom,master-id = <86>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART2_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
status = "disabled";
};
qcom-ipq40xx-ap.dk04.1
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1";
compatible = "qcom,ipq40xx-apdk04.1", "qcom,ipq40xx";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256MB */
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd1@87000000 {
/* Reserved for other subsystem */
reg = <0x87000000 0x500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
/* Reserved for other subsystem */
reg = <0x87B00000 0x500000>;
no-map;
};
};
chosen {
bootargs-append = " clk_ignore_unused";
};
};
&soc {
pinctrl@0x01000000 {
serial_0_pins: serial0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
led_0_pins: led0_pinmux {
mux_1 {
pins = "gpio36";
function = "led0";
bias-pull-down;
};
mux_2 {
pins = "gpio40";
function = "led4";
bias-pull-down;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
uart1_pins: uart1_pinmux {
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
function = "blsp_spi0";
bias-disable;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
sd_0_pins: sd_0_pinmux {
sd0 {
pins = "gpio23";
function = "sdio0";
drive-strength = <10>;
};
sd1 {
pins = "gpio24";
function = "sdio1";
drive-strength = <10>;
};
sd2 {
pins = "gpio25";
function = "sdio2";
drive-strength = <10>;
};
sd3 {
pins = "gpio26";
function = "sdio3";
drive-strength = <10>;
};
sdclk {
pins = "gpio27";
function = "sdio_clk";
drive-strength = <16>;
};
sdcmd {
pins = "gpio28";
function = "sdio_cmd";
drive-strength = <10>;
};
sd4 {
pins = "gpio29";
function = "sdio4";
drive-strength = <10>;
};
sd5 {
pins = "gpio30";
function = "sdio5";
drive-strength = <10>;
};
sd6 {
pins = "gpio31";
function = "sdio6";
drive-strength = <10>;
};
sd7 {
pins = "gpio32";
function = "sdio7";
drive-strength = <10>;
bias-disable;
};
};
ts_0_pins: ts_0_pinmux {
mux_1 {
pins = "gpio34";
output-high;
};
mux_2 {
pins= "gpio35";
input-enable;
bias-pull-up;
};
};
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "ok";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "ok";
};
uart1:uart@78b0000 {
pinctrl-0 = <&uart1_pins>;
pinctrl-1 = <&uart1_pins>;
pinctrl-names = "default", "sleep";
status = "disabled";
};
spi_0: spi@78b5000 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <24000000>;
use-default-sizes;
};
};
tcsr: tcsr@194b000 {
status = "ok";
};
usb3_ss_phy: ssphy@0 {
status = "ok";
};
dummy_ss_phy: ssphy@1 {
status = "ok";
};
usb3_hs_phy: hsphy@a6000 {
status = "ok";
};
usb2_hs_phy: hsphy@a8000 {
status = "ok";
};
usb3: usb3@8a00000 {
status = "ok";
};
usb2: usb2@6000000 {
status = "ok";
};
i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&i2c_0_pins>;
pinctrl-1 = <&i2c_0_pins>;
pinctrl-names = "i2c_active", "i2c_sleep";
status = "ok";
qca_codec: qca_codec@12 {
compatible = "qca,ipq40xx-codec";
reg = <0x12>;
status = "disabled";
};
lcd_ts: lcd_ts@40 {
compatible = "qca,gsl1680_ts";
reg = <0x40>;
status = "disabled";
};
};
qcom_crypto: qcrypto@8e20000 {
status = "ok";
};
qcom_cedev: qcedev@8e20000 {
status = "ok";
};
pcie0: qcom,pcie@80000 {
status = "ok";
perst-gpio = <&tlmm 57 0>;
wake-gpio = <&tlmm 50 0>;
clkreq-gpio = <&tlmm 39 0>;
};
qcom: ledc@1937000 {
status = "ok";
pinctrl-0 = <&led_0_pins>;
pinctrl-names = "default";
};
ess-switch@c000000 {
switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */
switch_initvlas = <
0x0007c 0x54 /* PORT0_STATUS */
>;
led_source@0 {
source = <0x1>; /*source id 1 */
mode = "normal"; /*on,off,blink,normal */
speed = "all"; /*10M,100M,1000M,all */
freq = "auto"; /*2Hz,4Hz,8Hz,auto*/
};
led_source@1 {
source = <0x4>; /*source id 4 */
mode = "normal"; /*on,off,blink,normal */
speed = "all"; /*10M,100M,1000M,all */
freq = "auto"; /*2Hz,4Hz,8Hz,auto*/
};
led_source@2 {
source = <0x7>; /*source id 7 */
mode = "normal"; /*on,off,blink,normal */
speed = "all"; /*10M,100M,1000M,all */
freq = "auto"; /*2Hz,4Hz,8Hz,auto*/
};
led_source@3 {
source = <0xa>; /*source id 10 */
mode = "normal"; /*on,off,blink,normal */
speed = "all"; /*10M,100M,1000M,all */
freq = "auto"; /*2Hz,4Hz,8Hz,auto*/
};
led_source@4 {
source = <0xd>; /*source id 13 */
mode = "normal"; /*on,off,blink,normal */
speed = "all"; /*10M,100M,1000M,all */
freq = "auto"; /*2Hz,4Hz,8Hz,auto*/
};
};
vccq_sd0: regulator@0 {
compatible = "qcom,regulator-ipq40xx";
regulator-name = "SD0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
states = <3000000 0x3
1800000 0x1>;
reg = <0x01948000 0x4>;
mask = <0x3>;
};
sdhci@7824000 {
status = "ok";
pinctrl-0 = <&sd_0_pins>;
pinctrl-names = "default";
vqmmc-supply = <&vccq_sd0>;
cd-gpios = <&tlmm 22 0x1>;
sd-ldo-gpios = <&tlmm 33 0x1>;
};
qcom,nand@7980000 {
status = "disabled";
};
gpio_keys {
compatible = "gpio-keys";
button@1 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
};
};
};